CYD ESP32-8048S050 Development Board Pinout and Technical Specifications
Code name: CYD_ESP32_8048S050
Manufacturer: CYD (Cheap Yellow Display)
CYD ESP32-8048S050 development board is based on esp32s3 microcontroller and uses xtensa architecture. This development board has a maximum CPU frequency of 240 MHz and a flash size of 32Mbit.
🔗 Quick Links
🛒 Price
📝 CYD ESP32-8048S050 Description
🚀 The CYD ESP32-8048S050 is a budget-friendly ESP32-S3-based development board, commonly referred to as a Cheap Yellow Display (CYD). It features integrated WiFi, Bluetooth 4.2, and a 5.0-inch 800x480 LCD, making it an excellent choice for affordable IoT and embedded display projects. ⚡
📡 With support for 802.11 B/G/N WiFi and Bluetooth 4.2 (BLE), this board is well-suited for wireless applications.
💾 Equipped with 32Mbit SPI Flash, multiple ADC, DAC, I2C, SPI, UART, PWM, and I2S interfaces, it offers a versatile platform for various embedded projects.
📊 CYD ESP32-8048S050 Specs
Below you can find the specifications of CYD ESP32-8048S050, such as features, connectivity options, and CYD ESP32-8048S050 technical specs.
✨ Features
- 21 digital IO pins
- 22 external interrupt pins
- 6 analog input pins
- 14 PWM pins
🖥 Display
- Type: 5.0-inch LCD
- Resolution: 800x480
🖥️ Display
- Type: 5.0-inch LCD
- Resolution: 800x480
🛰️ Connectivity
- WiFi: 802.11 b/g/n (2.4 GHz)
- Bluetooth: 5.0
- BLE: 5.0
📐 Technical specs
| Microcontroller | esp32s3 |
| Clock Speed | 240 MHz |
| Flash size | 32Mbit |
| PSRAM Size | None |
| Architecture | xtensa |
🔌 CYD ESP32-8048S050 Pinout
⚠️ Pins to Avoid or Use with Caution
Some pins are reserved for critical functions like bootstrapping, JTAG debugging, USB communication, and flash memory operations. Misusing these pins may lead to boot failures, programming issues, USB conflicts, or disruptions in flash storage. Below is a list of pins to avoid or use with caution, categorized for clarity:
- 🛠️ Strapping Pins (Boot Mode & System Behavior) - These pins control boot behavior and flash voltage selection. Pulling them high or low at reset can impact boot mode selection, voltage settings, or debugging access. Avoid altering their state unless necessary.
- 🔗 JTAG Debugging Pins - JTAG is used for low-level debugging and programming. If JTAG is enabled, these pins must remain dedicated to it. Repurposing them as GPIO can disable JTAG debugging features.
- 🔌 USB Communication Pins - These pins are used for USB Serial/JTAG communication. If USB debugging or communication is required, they should not be reassigned as GPIO.
- ⚡ Flash Memory & SPI Pins - Certain GPIOs are hardwired to SPI flash memory and PSRAM. Using them as standard GPIOs may result in system instability, corrupted storage, or boot failure.
- 📡 UART Serial Communication Pins - By default, these pins are used for serial debugging, console output, and firmware uploads. Repurposing them for general I/O may break UART programming or debugging capabilities.
| PIN | Label | Reason | Function |
|---|---|---|---|
| IO3 | GPIO3 | Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface. | 🛠️ Strapping |
| IO19 | USB_D- | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | 🔌 USB |
📌 Key Takeaway:
- Before using any GPIO, check if it is assigned a critical function.
- Avoid using bootstrapping pins unless you're modifying boot behavior intentionally.
- If JTAG debugging is needed, ensure its pins remain free.
- USB and Flash-related GPIOs should remain dedicated unless you disable their default functions.
✅ Pins Safe to use
- 🔹 IO1
- 🔹 IO2
- 🔹 IO16
- 🔹 IO17
- 🔹 IO18
- 🔹 IO21
- 🔹 IO22
Unlike restricted pins, these GPIOs are not tied to essential system functions like 🛠️ bootstrapping, 🔌 USB communication, 🔗 JTAG debugging, or ⚡ SPI flash memory, making them the best choices for custom applications and general use.
Why Are These Pins Safe?- Not involved in bootstrapping → These GPIOs do not affect the device’s boot mode or system startup.
- Not linked to flash memory or PSRAM → They won’t interfere with storage or memory access.
- Not dedicated to USB or JTAG → They remain free for general use without affecting debugging or programming.
- No special hardware connections → Unlike some pins that are internally wired to system functions, these remain freely assignable.
🗺️ CYD ESP32-8048S050 External Pins Mapping Functions
Below you can find the CYD ESP32-8048S050 pinout. This development board provides 21 digital IO pins, out of which 22 can be used as an external interrupt pins , 6 as analog input pins and 14 pins have Pulse-Width Modulation (PWM) .
| Pin | Function | ESP Pin | Input/Output | Description |
|---|---|---|---|---|
| 1 | 3V3 | 3.3V | POWER OUTPUT | 3.3V power output |
| 2 | GND | GND | POWER GROUND | Ground connection |
| 3 | 5V | 5V | POWER INPUT | 5V power input |
| 4 | IO1 | GPIO1 | BIDIRECTIONAL | GPIO, ADC, I2C |
| 5 | IO2 | GPIO2 | BIDIRECTIONAL | GPIO, ADC |
| 6 | IO3 | GPIO3 | BIDIRECTIONAL | GPIO, ADC |
| 7 | IO16 | SPI_CS | BIDIRECTIONAL | GPIO, SPI Chip Select |
| 8 | IO17 | SPI_D | BIDIRECTIONAL | GPIO, SPI Data |
| 9 | IO18 | SPI_CLK | BIDIRECTIONAL | GPIO, SPI Clock |
| 10 | IO19 | SPI_Q | BIDIRECTIONAL | GPIO, SPI Q |
| 11 | IO21 | UART_TX | OUTPUT | GPIO, UART TX |
| 12 | IO22 | UART_RX | INPUT | GPIO, UART RX |
🛠️ Default Tools
| Bootloader tool | esptool_py |
| Uploader tool | esptool_py |
| Network uploader tool | esp_ota |
| Bootloader address | 0x1000 |
| Flash mode | dio |
| Boot mode | qio |
| PSRAM type | |
| Maximum upload size | 1280 Kb (1310720 B) |
| Maximum data size | 320 Kb (327680 B) |
The CYD ESP32-8048S050 development board by default uses esptool_py uploader tool, esp_ota network uploader tool for Over-the-air (OTA) uploads and esptool_py bootloader tool. The bootloader starts at address "0x1000". Flash mode and boot mode for CYD ESP32-8048S050 development board by default is dio and qio respectively.
